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Interpreted and validated electrical schematics, block diagrams, and system-level requirements across advanced semiconductor nodes (5nm–12nm). Supported design flows, collaborating with layout and circuit teams to maintain consistency with design rules (DRC, LVS) and ensured version control and documentation accuracy.
Analyzed complex block architectures and supported EDA flow integration and tool usage across Synopsys and Cadence platforms. Coordinated with cross-functional teams for design reviews and issue resolution.
Gained hands-on experience interpreting schematics, timing reports, and design validation. Developed strong understanding of engineering documentation, version control, and electrical consistency checks.
Conducted circuit-level verification, EMIR checks, and schematic-layout validation using Cadence Virtuoso, ensuring compliance with electrical design requirements.